This is a brief explanation about the firmware for MASSIBO digitizer and data sender.

<aside> 💡 Tip: Don’t touch the Ethernet CORE

</aside>

Structure of the firmware Architecture

The HDL modules hierarchy is organized as follows:

graph TD;
    A["Top_level (daphne_massibo)"] --> B["sys_timing_endpoint"];
    A --> C["Ethernet Core"];
    A --> D["AFE"];
    A --> E["ETH_MUX"];
    A --> F["Led_contoller"];
    B --> B1["Clock_manager (MMCM)"];
    C --> C1["PCS_PMA"];
    C --> C2["ETH_inst"];
    D --> D1["AFE_inst"];
    D --> D2["hpf_pedestar_reco"];
    D --> D3["Trig_Manager"];
    D --> D4["FIFOs (DATA/Ts)"];
    D3 --> D33["FIFO_CTRL"]

Each module has specific responsibilities:

• Sys_timing_endpoint: Handles system clock generation and distribution.
• Ethernet Core: Manages network communication protocols.
• AFE: Controls the analog-to-digital conversion, trigger, and data storage process.
• ETH_MUX: Handles the data sender.

The modules communicate through well-defined interfaces to ensure proper data flow and synchronization.

Sys_timing_endpoint

entity endpoint is
  Port ( 
    --Inputs
    reset_n:    in  std_logic; -- active LOW reset from the microcontroller
    sysclk_p:   in  std_logic; -- system clock LVDS 100MHz from local oscillator
    sysclk_n:   in  std_logic; -- (note internal 62.5MHz clock is generated from this 100MHz clock)  
	
	--Outputs
    sys_clk437_5                    : out std_logic; 
    sys_clk200                      : out std_logic; 
    sys_clk62_5                     : out std_logic; 
    sys_clk31_25                    : out std_logic; 
    sys_clk15_625                   : out std_logic;
    sys_clk41_66                    : out std_logic;
    afe_clk_p,afe_clk_n             : out std_logic; 
    --Status Outputs
    locked                          : out std_logic
 
  );
end endpoint;

For generating the different frequencies, it is necessary to use the clock wizard from the IP of Xilinx.

<aside> 💡 Tip: To change the output clock frequency, you can modify the different multiplication numbers by hand, but is you are not an expert on that, the suggestion is: create a new IP_clock_core or modify the existing IP_clock_core.

</aside>

Ethernec Core

This module is from Fermilab for DAPHNE communication.

AFE